The present invention relates to an access sequence controller for a memory unit. More particularly, the invention relates to an access sequence controller for a memory unit of a data processing system controlling the correspondence between the sequence of a vector element, which is the equivalent of the descriptor of the vector component, which indicates the element number in terms of a vector and the access sequence for the memory unit. This is accomplished by providing a queue register for controlling the access to the memory unit for the purpose of reading out each element data, which is the value of each component, of a vector. The element data elements of the vector compose the vector from the memory unit or constitute the vector stored in the memory unit.
In the field of scientific calculation, array data such as, for example, vector or matrix data, and string data are frequently used. Therefore, various ideas have been employed from both aspects of hardware and software in order to realize the arithmetic operation of such data at a high speed. However, particularly in the subjects of weather calculation, linear planning, and structure calculation, large scale array data processing becomes an important problem. For such calculation, several hundreds hours are required even when an ultra-high speed computer system is utilized.
It is assumed that an arithmetic operation of vectors B and C is included in the array date processing. When each vector is considered, respectively, as B=(b.sub.0,b.sub.1, . . . , b.sub.n) and C=(C.sub.0,C.sub.1, . . . , C.sub.n), each of b.sub.0,b.sub.1, . . . , b.sub.n and C.sub.0,C.sub.1, . . . , C.sub.n is an element data. The element data b.sub.0 and C.sub.0 are considered the 0th element sequence, the element data b.sub.1 and C.sub.1 are considered the first element sequence, and the element data b.sub.n and c.sub.n are considered the nth element sequence.
In addition, the domain in the memory unit where each element is stored is called the element address. Therefore, in actual operation, first b.sub.0,b.sub.1, . . . , b.sub.n and C.sub.0,C.sub.1, . . . , C.sub.n are read out from the memory unit using the element address. Thus, operations of b.sub.0 and C.sub.0, b.sub.1 and C.sub.1, . . . , b.sub.n and C.sub.n are performed respectively. However, it is not efficient to make access individually to b.sub.0,b.sub.1,b.sub.2, . . . , b.sub.n concerning vector B and C.sub.0,C.sub.1,C.sub.2, . . . , C.sub.n concerning vector C for readout of the element data from the memory unit, and to individually perform the operation of b.sub.0 and C.sub.0, b.sub.1 and C.sub.1, . . . , b.sub.n and C.sub.n according to the readout sequence, because of the following reasons.
When the memory unit is divided into several domains, areas or devices so that access can be made independently from several units, the domain storing b.sub.0 cannot be accessed immediately, because that domain is accessed by the other units. However, the domain storing b.sub.1 can be accessed immediately in some cases. In such a case, if the access sequence is fixed, b.sub.0 is read out after the access from the other units, then access is made to the memory unit for reading out b.sub.1, thus resulting in queuing time. For this reason, it is not desirable, from the viewpoint of the efficiency in access to the memory unit, to fix the readout sequence.
In order to eliminate such queuing time it is only necessary to try an access to the memory unit for element data sequentially, if possible, irrespective of the sequence of b.sub.0,b.sub.1 . . . , b.sub.n, as long as there is a vacant domain in the memory unit.
Readout operation is performed for the vector C in a similar manner and calculation is necessary for complete vectors. In this case, however, it is necessary to manage a specific access which corresponds to an element in a specified number.
An object of the invention is to provide an access sequence controller for a memory unit, which controller is especially suitable for array data processing.
Another object of the invention is to provide an access sequence controller for a memory unit, which controller provides access to a memory unit for element data sequentially irrespective of the sequence of element data.
Still another object of the invention is to provide an access sequence controller for a memory unit, which controller functions efficiently, effectively and reliably to provide sequential access to element data in a memory unit.